1. Field of the Invention
The present invention relates to a semiconductor device manufacturing method, a semiconductor device, a semiconductor simulation method and a simulator, and more particularly to improve performance of lumped elements of devices and fabrication yield in scaled large scale integration (LSI), in conjunction with a computer aided design (CAD) tool.
2. Description of the Prior Art
Semiconductor design and fabrication have a wide variety of issues, relating to LSI fabrication, process design, system design, device design, and so on. Problems underlying the current process/device/system design phase are described.
First, a historical overview and the current status of the semiconductor industry and LSI device research and development phase are described. The semiconductor industry has continued to prosper as the result of continuous improvement of productivity and creative research throughout its history. It is believed that these trends will continue into the foreseeable future. It is instructive to quantitatively sketch the time evolution of high-tech consumer electronics in terms of product size. In the past decade, for example, the overall volume of mobile communications and personal computers has been reduced by an order of magnitude or more, with corresponding weight savings being realized. The number of transistors per microprocessor chip and per memory chip as a function of year is shown in FIG. 1. The time-dependent increase in the number of transistors on microprocessor and memory integrated circuit chips is shown in a logarithmic scale.
Regarding device size in the chips, the gate length of the devices and the isolation area size have been reduced as the number of transistors has increased. Roughly speaking, a typical design rule of a first phase of 256M DRAM (Dynamic Random Access Memory) has been around 0.25 microns. As a common language in the LSI industry and academia, the phrase xe2x80x98design rulexe2x80x99 is used as technology generation. xe2x80x98LSIxe2x80x99 is an integrated science and technology across large areas as its word literally says; circuit technology, device technology, mathematics, chemistry, physics, electrical engineering, computer simulation, and so on. So, a typical design xe2x80x98rulexe2x80x99 as technology generation specification is a very useful and convenient index in order to share and own a common meaning among engineers. FIG. 2 shows the typical technology parameters as a function of LSI generation. A design rule is shown in terms of DRAM capacity, year of the first production and so on. From FIG. 2, it is understood that the continual drive towards smaller feature size in device fabrication results in tighter design criteria and increased complexity of equipment used in semiconductor processing.
Basic research and developments have already started intensively for 0.13 microns or more scaled-down device/process design phase in universities, many LSI companies, and institutions all over the world. FIG. 3 show a cross section image of typical recent devices, which is appeared in a reference, J. G. Ryan, R. M. Geffken, N. R. Poulin, and J. R. Paraszczak, IBM J. Res and Develop. 39, 371 (1995). Abbreviations of M1 to M5 are metal layers. At the bottom layer of FIG. 3, are MOS devices. There is a need to contact and interconnect (M1 to M4) among all of the semiconductor electrodes, i.e., source, drain, and gate, to other components and devices on the chip. The highest level (M5) is composed for bus-bars that carry current to chip contact pads.
FIG. 4 shows the number of metal layers as a function of technology generation. The signal delay among a large number of devices is minimized, so eventually a multi-layered structure of metallization was used. It can be seen from FIG. 4 that with reducing design rule, more metal layers are needed. The increase of the integration density, while maintaining the same RC signal delay leads to a strong increase of the number of the metal layers. This trend is mitigated by introducing new materials. Historically, SiO2 has been well adopted for passivation films and interlayer dielectric films, and aluminum has also been well accepted as an interconnect metal. In FIG. 4, some of the improvements are also presented; such as introducing Cu/SiO2, and some low epsilon materials. As overviewed above, the semiconductor industry has continued to prosper as the result of continuous improvement of productivity and creative research throughout its history. Also intensive research and developments have already started for 0.17 micron or more scaled-down device/process design phase.
As background, the LSI fabrication process is described. The LSI fabrication process has been composed basically of diffusion, silicidation, oxidation, chemical vapor deposition (CVD), ion implantation, etching and so-forth. These processes have been done repeatedly on semiconductor silicon substrates.
Before this LSI device fabrication, photomasks are made based on desired design rules. The design rules provide a necessary communication link between circuit designer and process engineer during the manufacturing phase. The main objective associated with layout rules is to obtain a circuit with optimum yield (functional circuit versus nonfunctional circuits) in as small an area as possible without compromising the reliability of the circuit. In general, design rules have represented the best possible compromise between performance and yield. The more conservative the rules are, the more likely it is that the circuit will function. However, the more aggressive the rules have been, the greater the probability of improvements in circuit performance. This improvement has been at the expense of yield. Based on these huge efforts, LSI has been continuously prosperous up to now.
Computer simulation tools for reducing time-around-time in trial and error phase are described. FIG. 5 shows an overview of the process flow of the simulator SUPREM (Stanford University Program for IC Process Engineering Models) which is one of the most famous and widely used simulators. Oxidation, diffusion, ion implantation, etching processes which are mentioned above, have been implemented in computer simulation programs based on chemical/physical models as subroutines. Most of the trial and error in research and development phase are done in computer programs. One can estimate and predict easily impurity profiles and final device structure in advance of actual fabrication. Once some impurity profiles are obtained in the device, then, device characteristics can also be calculated. FIG. 6(a) shows a three-dimensional graph of the potential plotted from a conventional device simulation solution based on estimated impurity profiles. Moreover, FIG. 6(b) shows a graph of subthreshold current in the simulated MOSFET (metal oxide semiconductor field effect transistor). So, eventually, the device characteristic for individual unit device can be estimated from an input process sequence. These CAD tools such as SUPREM to have now been indispensable in LSI fabrication lines.
FIG. 7 is a flow chart showing a typical conventional design process phase for an analog integrated circuit for telecommunications. Here, the xe2x80x98simulationxe2x80x99 is also seen. The task of designing an analog or digital integrated circuit includes many steps. FIG. 7 illustrates the general approach to the design of an integrated circuit. The major steps in the conventional design process are:
1) definition,
2) synthesis or implementation,
3) simulation or modeling,
4) geometrical description,
5) simulation including the geometrical parasitics,
6) fabrication, and
7) testing and verification.
The circuit designer is responsible for all of these steps except fabrication. The first major task is to define and synthesize the design. This step is crucial since it determines the performance capability of the design. When this task is completed, the designer must be able to confirm the design before it is fabricated. This leads to the second major taskxe2x80x94using simulation methods to predict the performance of the circuit. At this point, the circuit designer may iterate using the simulation results to improve the circuit""s performance. Once satisfied with this performance, the designer can attack the third major taskxe2x80x94a geometrical description (layout) of the circuit. This geometrical description typically consists of a computer database of variously shaped rectangles or polygons (in the x-y plane) at different levels of space (in the z-direction); the layout is intimately connected with the electrical performance of the circuit. Once the layout is finished, it is necessary to include the geometrical effects in a second simulation. If the results are satisfactory, the circuit is ready for fabrication. Then the designer is faced with the last major taskxe2x80x94determining whether the fabricated circuit meets the design specifications. If the designer has not carefully considered this step in the overall design process, it is often impossible to test the circuit and determine whether or not the specifications have been met.
So, it is understood that xe2x80x98simulationxe2x80x99 has now been inevitable in LSI manufacturing phase. Computer programs that simulate the performance of an electronic circuit provide a simple, cost-effective way of confirming the intended operation prior to circuit performance. Such computer programs have revolutionized the electronics industry, leading to the development of today""s high-density monolithic circuit schemes such as VLSI (Very Large Scale Integration).
As background, the simulator named SPICE (Simulation program with integrated circuit emphasis) is now described. One of the typical standard manuals is SPICE second edition by G. W. Roberts and A. S. Sedra, Oxford University Press (1997), ISBN 0-19-510842-6. The SPICE, the de facto industrial standard for computer-aided circuit analysis, was developed in the early 1970s at the University of California, Berkeley. Although other programs for computer-aided circuit analysis exist and are used by many different electronic design groups, SPICE is the most widespread. Until recently, it was largely limited to mainframe computers on a time-sharing basis, but today various versions of SPICE are available for personal computers. In general, these other programs use algorithms slightly different from SPICE""s for performing the circuit simulations, but many of them adhere to the same input description, elevating the SPICE input syntax to a programming language.
Now, a current circuit simulation methodology is described. FIG. 8 shows a typical MOSFET call in a SPICE simulator. The SPICE netlist fragment specifies an n-channel transistor element card M1, which uses an NMOS model called NFET. The terminal connections specify the drain is connected to node 4, the gate is connected to node 3, the source is connected to node 5, and the substrate is connected to node 0. , M1 is a 4 microns (W=4U) wide by 1 micron (L=1U) long transistor with source and drain areas of 15 square microns (AS=15P, AD=15P). The source and drain peripheries are 11.54 microns (PS=11.5U, PD=11.5U). The start of the MODEL statement is signified by the MODEL line. The second line on the model card specifies the thin-oxide thickness (TOX=200E-8). This allows SPICE to calculate the voltage-dependent gate capacitance. The maximum capacitance values is
Cg=Wxc3x97Lxc3x97Cox=4xc3x971xc3x9717xc3x9710xe2x88x924 pF=0.0068 pF
As described above, a MOS structure is created by superimposing a number of layers of conducting, insulating, and transistors forming materials. It has been further demonstrated that in a conventional silicon gate process, a MOS device requires a gate-forming region and a source/drain-forming region, which consists of diffusion, poly silicon, and metal layers. Each layer has both a resistance and a capacitance that are fundamental components in estimating the performance of a circuit or system. The metal layers also have inductance characteristics that are important when considering I/O (input output) behavior but usually assumed to be negligible for most on-chip circuits.
Models are discussed that assist in the understanding of system behavior and that provide the basis whereby systems performance, in terms of signal delays and power dissipation, can be estimated from a simulation viewpoint. The issues to be described herein are:
resistance, capacitance, and inductance calculations,
delay estimations,
determination of conductor size for power and clock distribution,
power consumption,
charge sharing mechanism,
design margining,
reliability,
effects of scaling, so-on
The resistance of a uniform slab of conducting material may be expressed as
R=(xcfx81/t)(l/w)
where xcfx81=resistivity, t=thickness, l=conductor length, and w=conductor width. The expression may be written as R=Rs(l/w)(ohms) where Rs is the sheet resistance having units of xcexa9/square.
Many times during the course of a layout, nonrectangular shapes are used (for instance, the corners of wires). The resistance of these shapes requires more elaborate calculations than that for simple rectangular regions. One method of calculating the resistance is to break the shape in question into simple regions, for which the resistance may be calculated, as shown in FIG. 9. This has been an innovative work, which was published in IEEE Transactions on computer-aided design, vol. CAD-2, No.3(1983)145 by Mark Horowitz and Robert W. Dutton. However, the device structure has been now not so smooth or plain (described below). So, it is now very difficult to estimate realistically the value of resistance.
FIG. 10 shows the typical circuit symbols for parasitic capacitance in SPICE modeling. For convenience for calculation, equivalent circuit models have been implemented in SPICE. The values, Cgd, Cdb, Csb, Cgb, Cgs, are capacitance between gate and drain, capacitance between drain and bulk, capacitance between source and bulk, capacitance between gate and bulk, capacitance gate and source, respectively. These values are quite important for precise estimation for timing simulation in SPICE. However, these have been adjustable values. This is one of the reasons why future LSI developments for 0.07 microns or more scaled have now been retarded.
Contacts and vias also have a resistance associated with them that is dependent on the contacted materials and proportional to the area of the contact. This is another reason why future LSI developments for 0.07 microns or more scaled have now been retarded.
As described above, the dynamic response (e.g., switching speed) of MOS systems is strongly dependent on the parasitic capacitance associated with the MOS device and interconnection capacitance that are formed by metal, poly, and diffusion wire (often called xe2x80x98runnersxe2x80x99) in concert with transistor and conductor resistances. The total load capacitance on the output of a CMOS gate is the sum of:
gate capacitance (of other inputs connected to the output of the gate),
diffusion capacitance (of the drain regions connected to the output), and
routing capacitance (of connections between the output and other inputs)
Understanding the source of parasitic loads and their variation is essential in the design process, where system performance in terms of the speed of the system form part of the design specification. FIG. 11 shows typical total gate capacitance of a MOS transistor as a function of Vgs. From these figures, it is seen that the capacitance vales also depend on Vds. FIG. 12 shows switching characteristics for a CMOS inverter; FIG. 12a shows circuit waveforms; FIG. 12b shows trajectory of n-transistor operating point during switching. FIG. 13 shows the conventional approximation of intrinsic MOS gate capacitance conversion.
A factor that emerges from equation, R=(xcfx81/t)(l/w) is that, as the diffusion area is reduced (through scaling, discussed below), the relative contribution of the peripheral capacitance becomes more important.
Other design phase difficulties exist. The propagation of a signal along a wire depends on many factors, including the distributed resistance and capacitance of the wire, the impedance of the driving source, and the load impedance. For very long wires with appreciable sheet resistance propagation delays caused by distributed resistance, capacitance (RC) in the wiring layer can dominate. This is indeed also related to the content in FIG. 4, described above. The switching speed of CMOS gates is limited by the time taken to charge and discharge the load capacitance CL. An input transition results in an output transition that either charges CL toward VDD or discharges CL toward VSS.
Before proceeding, however, some terms are defined:
rise time, tr,
fall time, tf,
delay time td,
Typical delay times for various technology nodes are illustrated in FIG. 14, and the approximations of intrinsic MOS gate capacitances are listed in FIG. 13. In FIG. 14, the x-axis shows xe2x80x98technology nodesxe2x80x99, which are similar to the above-mentioned xe2x80x98design rulexe2x80x99. FIG. 14 shows that the clock period (xe2x80x9cAxe2x80x9d), intrinsic gate delay (xe2x80x9cCxe2x80x9d), ecto wiring delay (xe2x80x9cDxe2x80x9d) and transistor transit time (xe2x80x9cExe2x80x9d) components decrease as the technology node decreases, while endo wiring delay (xe2x80x9cBxe2x80x9d) component increases. Even if a Cu/low k material is adopted, xe2x80x9cB*xe2x80x9d decreases lower than xe2x80x9cBxe2x80x9d; however, the component xe2x80x9cB*xe2x80x9d still dominates in more scaled devices. In order to continue to capture the productivity and performance advantages of scaled transistors, (such as matters shown in FIG. 1), the wiring imperative for GSI (gigascale integration) is quite succinct: xe2x80x98keep interconnects shortxe2x80x99. For the most part, this has not been the approach of the part due to the predominant influence of transistors on the key theoretical and practical limits on microchips. This era has concluded and future projections strongly indicate the necessity for xe2x80x98interconnect centricxe2x80x99 chip architectures for GSI. In other words, designing of wiring layout and wiring materials becomes an important issue more than transistor designing. The implications of this technological inversion are profound and should serve to foster radical changes in future architecture.
Now the difficulty of estimating periphery capacitance is described. FIGS. 15(a) through 15(d) show recent conventional DRAM cell structures, which have appeared in IBM Research and Development vol.39, No.1/2 (1995). From these figures, it can be seen that technology has now shifted in a three-dimensional stacked regime. Moreover, FIG. 16 shows a cross-sectional schematic structural view of a conventional pillar-shaped vertical transistor with surrounding gate. Here, it is easily understood that it would be very difficult to estimate overlap capacitance or peripheral capacitance and the like. So, a precise estimation of delay time or system design is not obtained in the model.
FIG. 17 shows a conventional peripheral capacitance estimation procedure and modeling in a TCAD (Technological Computer Aided Design) tool. The phase from TEG (test element group) test fabrication to check the system performance is still very much time-consuming. In order to verify the design or to evaluate reliability of product LSI, TEG is used together with LSI product. Because, in the product LSI, electric characteristics of each device cannot be measured directly. TEG consists of many components of product LSI such as elemental circuit, devices, conductors, and so-forth. Moreover, conventional TCAD now faces a huge barrier not previously experienced. Generally, xe2x80x98TCADxe2x80x99 signify specific simulators used for process/device designing of semiconductor devices, such as process simulator, device simulator, capacitance simulator between conductors, and so on. Therefore, the only concentration has been on material developments for wiring, developing interconnect materials, more multi-level interconnect layered structures, and so-forth. FIG. 4 shows this situation, as described above. Moreover, generally, SPICE simulator and most of the device simulators extract the parasitic capacitance component in an equivalent circuit method. So, results have been reported such as CGD/CGS calculation with only considering shape and parasitic capacitance at a cross over point of interconnect with simple definition, etc. as shown in FIG. 17. The definition is the substrate is flat and Vsub=0. In order to predict dynamical interaction between the multi-layered interconnections and MOSFETs with considering current flow/electric potential in conductors, a new numerical treatment based on electromagnetism is indispensable. It is desirable that such a new treatment solve the three-dimensional problem.
For 0.07 microns device or more scaled down, RandD situation has been completely and suddenly changed. More attention is paid to total structure of the device itself, electromagnetic equation itself without simplification. It is desirable to overcome existing difficulties of CAD estimation, by estimating signal delay and wire length distribution. FIG. 18 shows a conventional procedure for LSI development.
The problems facing the development of GSI are that because the simulations use a simple equivalent circuit method, it is difficult to precisely estimate delay time, performance, and the like. Because there is a lack of synthesis analysis across the entire lumped element devices, such criteria apply only to the interconnect process. In GSI, each specific space such as between via hole and gate electrode, between neighboring gate electrodes, between gate electrode and active area of neighboring device, and the like, become closer and closer. Therefore, neighboring devices and conductors mutually affect each other. By not incorporating cross talking in the scaled device, the full development of scaled device design is still impeded.
Herein, an overview of the current situation of CAD phase is made with special attention to accuracy of the phase. As we have seen about SUPREM4, SPICE, and some other relevant aspects in FIGS. 5 and 6, 8, and 10, respectively. Some improvements are made to the existing inaccurate situation of SPICE compared to experimental results; such as A. Witzig, C. Schuster, P. Regli, W. Fichtner, xe2x80x9cGlobal modeling of microwave applications by combining the FDTD method and a general semiconductors device and circuit simulatorxe2x80x9d, IEEE Transaction on Microwave theory and techniques, vol-47, no.6, (1999) 919. However, basically, such improvements do not make direct coupling or self-consistency between charge transport due to Poisson equation and some other electromagnetic phenomena, and fail to address the phenomena observed in scaled devices, such as electromagnetic related cross-talk.
Presently, there has not yet been established a method in practice which solves electromagnetic dynamics interaction across wiring, transistors, capacitance, resistors, and so-on during system operations, that are problematic for the conventional equivalent circuit model.
FIG. 19 shows an overview of a conventional LSI fabrication/design CAD phase. Conventional CAD technology may be categorized as shown in the upper half of the figure.
A conventional process simulation is mainly still two-dimensional, and a conventional device simulation is two- or three-dimensional. So, for some complicated structured devices such as shown in the lower half of FIG. 19, it is very difficult to estimate lumped device characteristics. Patchwork of simulations in individual sections is performed. Conventional CAD technology can be categorized in terms of its basic equation as shown in the upper half of FIG. 20.
As shown, the conventional process simulation is mainly still in two-dimensional, and the device simulation is in two- or three-dimensions shown in FIG. 20.
In summary, although interest in peripheral inductive effects, cross talking between interconnect and devices and so-on have grown with recent growing demand for scaled system LSI and scaled Si-based RF communication circuits, incorporation of the physical phenomena of interconnects and devices into design tool development has been limited.
It is an object of the present inventions to provide
(1) a predictable novel simulation system and a simulation method which can simulate a circuit dynamic characteristics for a three-dimensional lumped electron device circuit including transistors, interconnects, capacitors, resistor regions, and more particularly which can simulate dynamic characteristics based on Maxwell""s equation coupled with Poisson""s equation applying to an entire region for the said three-dimensional lumped electron device circuit including transistors, interconnects, capacitors, resistor regions, and
(2) a semiconductor fabrication method using a predictable novel simulation system which can simulate a circuit dynamic characteristics for a three-dimensional lumped electron device circuit including transistors, interconnects, capacitors, diffusion region, and more particularly which can simulate dynamic characteristics based on Maxwell""s equation coupled with Poisson""s equation applying to an entire region for the said three-dimensional lumped electron device circuit including transistors, interconnects, capacitors, resistor regions.
The present invention provides an electronic circuit design simulator comprising a three-dimensional lump device element part, a three-dimensional visco-elastic process simulation part interlinked with a three-dimensional lump device element part, and a material design part interlinked with the three dimensional lumped device element part and a three-dimensional visco-elastic process simulation part. The three-dimensional visco-elastic process simulation part may comprise a visco-elastic model for device material, a non-equilibrium point defect diffusion model, and an anisotropic young modulus model. The three-dimensional visco-elastic process simulation part may also comprise elements for simulating a metal deposition process, a metal etching process, a silicon substrate oxidation process, a poly silicon film oxidation process, an ion implantation process, and an impurity diffusion process.
The three-dimensional lumped device element part may comprise any of a Poisson""s equation model, an electron continuity equation model, a hole continuity equation model, a Maxwell""s equations model, an eddy current equation model, and an Ohm""s law equation model.
The present invention may also provide an electronic circuit simulator comprising a mask pattern process sequence model, a material simulator, a three-dimensional process simulator coupled to the mask pattern sequence model in the material simulator, and an equation model coupled to the three-dimensional process simulator executing circuit model equations in response to the three-dimensional process simulator.
The present invention provides a simulation model that accounts for peripheral inductive effects and cross talking between interconnect and devices for scaled system LSI and scaled Si-based RF communication circuits.